有限状态自动机是拥有有限数量的状态，并且每个状态可以变换其他状态的数学模型。
A finite-state machine (FSM) or finite-state automaton (FSA, plural: automata), finite automaton, or simply a state machine, is a mathematical model of computation. It is an abstract machine that can be in exactly one of a finite number of states at any given time. The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition. An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition. Finite-state machines are of two types—deterministic finite-state machines and non-deterministic finite-state machines. A deterministic finite-state machine can be constructed equivalent to any non-deterministic one.
Mealy FSM（米利型有限状态机）
在Mealy机器中，输出取决于当前状态和当前输入。
三段式Mealy机器的图示及其建模如下：
module mealy_3processes(input clk, input reset, input x, output reg parity); reg state, nextstate; parameter S0=0, S1=1; always @(posedge clk or posedge reset) // always block to update state if (reset) state <= S0; else state <= nextstate; always @(state or x) // always block to compute output begin parity = 1'b0; case(state) S0: if(x) parity = 1; S1: if(!x) parity = 1; endcase end always @(state or x) // always block to compute nextstate begin nextstate = S0; case(state) S0: if(x) nextstate = S1; S1: if(!x) nextstate = S1; endcase end
endmodule
Moore FSM（摩尔型有限状态机）
在Moore机器中，输出仅取决于当前状态。
以下是使用Moore型有限状态机实现的奇偶校验器的状态图。与之关联模型如下所示。
module moore_3processes(input clk, input reset, input x, output reg parity); reg state, nextstate; parameter S0=0, S1=1; always @(posedge clk or posedge reset) // always block to update state if (reset) state <= S0; else state <= nextstate; always @(state) // always block to compute output begin case(state) S0: parity = 0; S1: parity = 1; endcase end always @(state or x) // always block to compute nextstate begin nextstate = S0; case(state) S0: if(x) nextstate = S1; S1: if(!x) nextstate = S1; endcase end endmodule
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